1. Field of the Invention
The invention relates to a fabrication method of a pixel structure. More particularly, the invention relates to a fabrication method of a pixel structure applying a low temperature poly-silicon thin film transistor (LTPS TFT).
2. Description of Related Art
Early fabrication of poly-silicon thin film transistor (poly-silicon TFT) adopts a solid phase crystallization (SPC) process, and a process temperature is up to 1000° C., so it is necessary to adopt a quartz substrate having a relatively high melting point. In addition, because the cost of the quartz substrate is much more expensive than that of the glass substrate, and under the situation that the size of the substrate is limited, only small-sized panel (approximately only 2 to 3 inches) can be developed in the past. Recently, as the laser technology continuously develops, excimer laser annealing (ELA) process is introduced into the poly-silicon TFT process.
The ELA process mainly uses the laser beam to irradiate an amorphous silicon layer (a-Si layer), such that the a-Si layer is recrystallized after melting to form a poly-silicon layer. All the processes of the poly-silicon TFT process adopting the ELA process can be finished under a temperature of 600° C., so the poly-silicon TFT formed by the process is also referred to as a low temperature poly-silicon TFT (LTPS TFT).
FIG. 1 is a conventional pixel structure 100 applying the LTPS TFT. In the pixel structure 100, a poly-silicon pattern 112 and a poly-silicon pattern 114 are formed on a glass substrate 102, and the poly-silicon pattern 112 includes a source region 112s, a drain region 112d, a channel region 112c, and a lightly doped region 112k located between the source region 112s and the channel region 112c and between the drain region 112d and the channel region 112c. A gate insulation layer 120 covers the poly-silicon pattern 112 and the poly-silicon pattern 114, and a gate pattern 132 and a lower electrode pattern 134 are located on the gate insulation layer 120 and respectively correspond to the above of the poly-silicon pattern 112 and the poly-silicon pattern 114. A protective layer 140 covers the gate pattern 132 and the lower electrode pattern 134, and a source pattern 152a and a drain pattern 152b are located on the protective layer 140, and are respectively connected to the source region 112s and the drain region 112d of the poly-silicon pattern 112 through the protective layer 140 and the gate insulation layer 120. In addition, an upper electrode pattern 154 is also disposed on the protective layer 140, and corresponds to the lower electrode pattern 134. A planarization layer 160 covers the source pattern 152a, the drain pattern 152b, and the upper electrode pattern 154, and the planarization layer 160 has a contact window 162. The pixel electrode 170 is located on the planarization layer 160, and is connected to the drain pattern 152b through the contact window 162.
However, the fabricating process of the aforementioned conventional pixel structure as shown in FIG. 1 is relatively complicated. Generally, six or more mask processes are required to form the pixel structure. In addition, the poly-silicon pattern 114, the gate insulation layer 120, the lower electrode pattern 134, the protective layer 140, and the upper electrode pattern 154 in FIG. 1 can form a storage capacitor. Nevertheless, the poly-silicon pattern 114 is shielded by the lower electrode pattern 134 and can not be doped in the doping process of forming the source region 112s and the drain region 112d, which leads to a poor conductive characteristic of the poly-silicon pattern 114 and restricts the design of the storage capacitor.